1. Field of the Invention
The present invention relates a non-volatile semiconductor memory device using a non-volatile transistor in a memory cell.
2. Description of the Related Art
In a non-volatile semiconductor memory such as an EPROM (erasable programmable read only memory), a memory cell conventionally consists of one transistor, and "1" or "0" level of data is determined by turning on or off a selected memory.
In recent years, a high-speed operation of a semiconductor memory has been required as the processing speed of a CPU is increased. In accordance with this, conventionally, several types of EPROMs capable of performing high-speed operations are disclosed in some literatures. For example, "A 25 ns 16K CMOS PROM using a 4-Transistor Cell" is described in the "ISSCC, DIGEST OF TECHNICAL PAPERS" in pp. 162-163 published in the United States on Feb., 1985, "A 23 ns 256K EPROM with Double-Layer Metal and Address Transition Detection" is described in the ISSCC, DIGEST OF TECHNICAL PAPERS" in pp. 130-131 published in the United States on Feb., 1985, and "16 ns CMOS EPROM" is issued in the subcommittee of the Institute of Electrical and Electronics Engineers of Japan, 1989.
Memory cells known as differential cells are applied to the EPROMs described in the above literatures. In the differential cell, a memory cell consists of at least two transistors. In a data write mode, the two transistors are set in two different states such as high and low states of a threshold voltage depending on an injection state of electrons. In a data read mode, readout potentials from the two transistors are compared by a sense amplifier to read out data.
The differential cell has a larger noise margin than that of a general conventional memory cell consisting of one transistor and operated such that a readout potential from a cell transistor is compared with an intermediate level serving as a reference potential. Therefore, the differential cell is advantageously suitable for a high-speed operation.
A pattern layout of the differential cell will be described below. Conventionally, the differential cell has a layout in which two transistors are arranged to be adjacent to each other.
FIG. 1 is a circuit diagram showing a read circuit of a conventional EPROM having a differential cell. As shown in FIG. 1, conventionally, a pair of bit lines BL and BL selected by two column selecting transistors 1-1 and 1-2 are arranged to be adjacent to each other. A plurality of bit lines BL are commonly connected to a transistor 2-1 serving as a transfer gate, and a plurality of bit lines BL having the same number as that of the bit lines BL are commonly connected to a pass transistor 2-2 serving as a transfer gate. The pass transistors 2-1 and 2-2 are connected to a sense amplifier 3. In the sense amplifier 3, the potentials of a pair of bit lines BL and BL selected by the column selecting transistors 1-1 and 1-2 are applied, and the potentials are compared with each other to detect readout data from a memory cell (not shown).
In the EPROM with the above arrangement, one memory cell consists of two transistors for respectively storing different signal levels, and the two transistors are arranged to be adjacent to each other. According to this pattern layout, the following problem is posed.
In FIG. 1, column selecting transistors 1-1 and 1-2 are difficult to be arranged. The size of a memory cell is minimized, and a pitch in a column direction has a minimum size. In this state, since two bit lines BL and BL must be parallelly arranged in a direction perpendicular to the column direction, it is very difficult to arrange the bit lines. In addition, even if the bit lines can be arranged as a pattern, since portions 4 where the bit lines cross each other are formed and one of two bit lines must be jumped over the other by using another wiring means such as a diffusion layer, the wiring pattern is complicated. Furthermore, since the wiring resistances of the bit lines are different from each other symmetry of the column selecting transistors is degraded.
With the above arrangement, symmetry of the differential cell is degraded. For example, a differential cell shown in FIG. 2A is known as an interleaved cell, and the interleaved cell consists of two staggered non-volatile transistors. FIG. 2B is an equivalent circuit diagram of FIG. 2A. In the memory cell in FIG. 2B, word lines WL are arranged to cross bit lines BL and BL. Since different signal levels must be read out from a pair of transistors to the pair of bit lines, one word line WL is commonly used for a pair of transistors MR and MR which are obliquely adjacent to each other through a source line SL in FIG. 2B.
In general, impurity ions are implanted in the channel regions of two transistors constituting a memory cell to control a threshold voltage, and a predetermined angle is given to the implantation direction upon the ion implantation to form a shallow channel region having good characteristics. For this reason, in an interleaved cell, since directions of implantation in the channel regions of two transistors constituting a 1-bit memory cell are different from each other when the directions are viewed from the sources of the two transistors, the transistors MR and MR, characteristics of which are preferably equal to each other, become different from each other in characteristics.
Since source lines wired to be in contact with the source regions are every several bit lines BL and BL alternately arranged, the positions of the source lines and the corresponding pair of transistors are not symmetrical. This arrangement is formed not only in the interleaved cell but in all differential cells in which bit lines BL and BL are alternately arranged.
As described above, in a conventional non-volatile semiconductor memory device, two transistors constituting a 1-bit memory cell are arranged to be adjacent to each other. Therefore, since a pair of bit lines must be alternately arranged, column selecting transistors are difficult to be arranged, characteristics of two transistors constituting the memory cell are disadvantageously different from each other.